The present invention relates generally to integrated circuits, and more specifically, to providing a scheme on how to integrate two-dimensional self-aligned super via (tall via) (V0) on self-aligned gate contact metal layer.
The back end of line (BEOL) is the second portion of integrated circuit fabrication where the individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, i.e., the metallization layer. Common metals are copper interconnect and aluminum interconnect. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.
General steps of BEOL may include silicidation of source/drain region usually considered as front end of line (FEOL) or middle of line (MOL). BEOL usually starts from material when copper (Cu) is used.